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electronic devices division multi-power supply r 5ve0 series application manual no.ea-021-9803
no tice 1. the products and the product specifications described in this application manual are subject to change or dis - continuation of production without notice for reasons such as improvement. therefore, before deciding to use the products, please refer to ricoh sales representatives for the latest information thereon. 2. this application manual may not be copied or otherwise reproduced in whole or in part without prior written con - sent of ricoh. 3. please be sure to take any necessary formalities under relevant laws or regulations before exporting or other - wise taking out of your country the products or the technical information described herein. 4. the technical information described in this application manual shows typical characteristics of and example application circuits for the products. the release of such information is not to be construed as a warranty of or a grant of license under ricoh's or any third party's intellectual property rights or any other rights. 5. the products listed in this document are intended and designed for use as general electronic components in standard applications (office equipment, computer equipment, measuring instruments, consumer electronic products, amusement equipment etc.). those customers intending to use a product in an application requiring extreme quality and reliability, for example, in a highly specific application where the failure or misoperation of the product could result in human injury or death (aircraft, spacevehicle, nuclear reactor control system, traffic control system, automotive and transportation equipment, combustion equipment, safety devices, life support system etc.) should first contact us. 6. we are making our continuous effort to improve the quality and reliability of our products, but semiconductor products are likely to fail with certain probability. in order prevent any injury to persons or damages to property resulting from such failure, customers should be careful enough to incorporate safety measures in their design, such as redundancy feature, fire-containment feature and fail-safe feature. we do not assume any liability or responsibility for any loss or damage arising from misuse or inappropriate use of the products. 7. anti-radiation design is not implemented in the products described in this application manual. 8. please contact ricoh sales representatives should you have any questions or comments concerning the prod - ucts or the technical information. june 1995
outline ...................................................................................................... 1 fea tures .................................................................................................... 1 applica tions ............................................................................................. 1 pin configura tion ................................................................................... 1 p a cka ge ..................................................................................................... 1 block dia grams ....................................................................................... 2 selection guide ....................................................................................... 2 pin description ........................................................................................ 3 optional mask version guide ............................................................... 4 description of ea ch circuit ................................................................. 5 absolute maximum ra tings ................................................................... 7 o verall chara cteristics ...................................................................... 7 explana tion of opera tion ................................................................... 17 test circuits (r 5ve001a,b,c) ............................................................... 20 typical chara cteristics (r 5ve001a) ................................................ 22 ?regulator section 1) output voltage vs. input voltage ............................................................................ 22 2) output voltage vs. output current .......................................................................... 23 3) dropout voltage vs. output current ......................................................................... 23 4) output voltage vs. temperature ............................................................................. 24 5) ripple rejection ............................................................................................. 24 6) line transient response 1 .................................................................................. 24 7) line transient response 2 .................................................................................. 25 8) supply current vs. input voltage ............................................................................ 26 9) supply current vs. temperature ............................................................................. 26 10) output voltage transient response for ?sw?input voltage step ......................................... 27 ?detector section 1) output voltage vs. input voltage ............................................................................ 28 2) output current vs. input voltage ............................................................................ 28 3) supply current vs. input voltage ............................................................................ 28 4) detected/released voltage vs. temperature ................................................................ 28 5) output delay time (fall) vs. load capacitance ............................................................. 29 6) output delay time (rise) vs. input voltage ................................................................. 29 7) output delay time (fall) vs. c d pin external capacitance .................................................. 29 8) output delay time (rise) vs. c d pin external capacitance ................................................. 29 typical chara cteristics (r 5ve001b) ................................................ 30 ?regulator section 1) output voltage vs. input voltage ............................................................................ 30 r 5ve o series applica tion manu al contents
2) output voltage vs. output current .......................................................................... 31 3) dropout voltage vs. output current ......................................................................... 31 4) output voltage vs. temperature ............................................................................. 32 5) ripple rejection ............................................................................................. 32 6) line transient response 1 .................................................................................. 32 7) line transient response 2 .................................................................................. 32 8) supply current vs. input voltage ............................................................................ 34 9) supply current vs. temperature ............................................................................. 34 10) output voltage transient response for ?sw?input voltage step ......................................... 35 ?detector section 1) output voltage vs. input voltage ............................................................................ 36 2) output current vs. input voltage ............................................................................ 36 3) supply current vs. input voltage ............................................................................ 36 4) detected/released voltage vs. temperature ................................................................ 36 5) output delay time (fall) vs. load capacitance ............................................................. 37 6) output delay time (rise) vs. input voltage ................................................................. 37 7) output delay time (fall) vs. c d pin external capacitance .................................................. 37 8) output delay time (rise) vs. c d pin external capacitance ................................................. 37 typical chara cteristics (r 5ve001c) ................................................ 38 ?regulator section 1) output voltage vs. input voltage ............................................................................ 38 2) output voltage vs. output current .......................................................................... 39 3) dropout voltage vs. output current ......................................................................... 39 4) output voltage vs. temperature ............................................................................. 40 5) ripple rejection ............................................................................................. 40 6) line transient response 1 .................................................................................. 40 7) line transient response 2 .................................................................................. 41 8) supply current vs. input voltage ............................................................................ 42 9) supply current vs. temperature ............................................................................. 42 10) output voltage transient response for ?sw?input voltage step ......................................... 43 ?detector section 1) output voltage vs. input voltage ............................................................................ 44 2) output current vs. input voltage ............................................................................ 44 3) supply current vs. input voltage ............................................................................ 44 4) detected/released voltage vs. temperature ................................................................ 44 5) output delay time (fall) vs. load capacitance ............................................................. 45 6) output delay time (rise) vs. input voltage ................................................................. 45 7) output delay time (fall) vs. c d pin external capacitance .................................................. 45 8) output delay time (rise) vs. c d pin external capacitance ................................................. 45 typical applica tion ............................................................................... 46 ? r 5ve00 1 ................................................................................................... 46 applica tion hints ................................................................................... 46 applica tion for the cellular phones ............................................. 47 ( r 5ve 0 :optional mask v er sion) p a cka ge dimensions .............................................................................. 49 t aping specifica tions ........................................................................... 49
mul ti-po wer suppl y 1 r 5ve 0 series outline the r 5ve 0 series are multi-power supply ics with high accuracy output voltage and detector threshold and with ultra low supply current by cmos process. each of these ics consists of four voltage regulators,two volt - age detectors and control switches.these ics can achieve the construction of an ideal power supply system in accordance with the user's mask option. output voltage and detector threshold can be independently set within each ic by laser trim. the package are of 16pin ssop(0.8mm pitch) and 16pin ssop(0.65mm pitch). ultra-low supply current broad operating voltage range ..................... 1.5v to 10.0v high accuracy output voltage and detector threshold ..................................................... 2.5% output voltage and detector threshold ........ stepwise setting with a step of 0.1v is possible (refer to selection guide) low temperature-drift coefficients of output voltage and detector threshold ............. typ. 100ppm/?c small dropout voltage ..................................... 50mv when i out is 80ma (regulators 1, 2) small package .................................................. 16pin ssop (0.8mm pitch) 16pin ssop (0.65mm pitch) direct connection to cpu is possible by an internal level shift circuit. fea tures applica tions ? power source system for hand-held communication equipment such as cellular phones and cordless telephones. power source system for battery-powered appliances. pin configura tion ? r 5ve00 1 v s e n 2 c d r e s e t d o u t i b c 1 g n d v d d c s w 3 r o u t 2 i b c 2 r o u t 1 2 v s e n 1 c s w 2 c s w 1 r o u t 4 1 3 4 6 8 5 7 9 1 0 1 1 1 6 1 5 1 3 1 4 1 2 r o u t 3
2 part number is designated as follows : r 5ve 0 ? ? part number - - - - - a b c d e selection guide in the r 5ve 0 series, standard ics and customized ics by mask option (hereinafter optional mask version ics) are available at the user's request. voltage settings for six circuits, four for regulators and two for detectors, can be designated. } code contents a designation of package type: s : 16pin ssop (0.8mm pitch) v : 16pin ssop (0.65mm pitch) b serial number for multi-power supply ic ( r 5ve) series: serial number for mask version: c 1 for standard ics. other numbers for optional mask version ics. d serial number for voltage setting: a to z are assigned in alphabetical order. (except i,o,q,x) designation of taping type: e ex. e1, e2 (refer to taping specifications) r 5ve 0 block dia grams c s w 1 v s e n 1 r e s e t c d g n d v s e n 2 l e v e l s h i f t r o u t 1 i b c 1 r e g u l a t o r 2 c s w 2 c s w 3 i b c 2 r o u t 2 r o u t 3 r o u t 4 d o u t l e v e l s h i f t l e v e l s h i f t r e g u l a t o r 1 r e g u l a t o r 3 d e t e c t o r 2 d e t e c t o r 1 d e l a y g e n e r a t o r v d d r e g u l a t o r 4 ? r 5ve00 1 v d d d e t e c t o r 2 c d g n d d o u t r e g u l a t o r 1 r o u t 1 i b c 1 r e s e t r o u t 2 i b c 2 r o u t 3 r o u t 4 r e g u l a t o r 2 r e g u l a t o r 3 r e g u l a t o r 4 d e t e c t o r 1 d e l a y g e n e r a t o r t q q r o n e s h o t p u l s e g e n e r a t o r t o b e n a m e d b y u e s r }
3 pin description pin no. symbol 1 r out 4 2 v sen 2 3 c d 4 reset 5 d out 6 r out 1 7 i bc 1 8 gnd 9 i bc 2 10 r out 2 11 csw1 12 csw2 13 csw3 14 v sen 1 15 r out 3 16 v dd description output pin for voltage regulator 4. sense pin for voltage detector 2. pin for external capacitor for delay time setting of voltage detector 2. output pin of voltage detector 2. nch open drain output. ??outputat detection. output pin of voltage detector 1. nch open drain output. ??output at detection. output pin of voltage regulator 1. connected to collector of pnp transistor. connected to base of external pnp transistor for voltage regulator 1 and controls base current. ground pin. connected to base of external pnp transistor for voltage regulator 2 and controls base current. output pin of voltage regulator 2. connected to collector of pnp transistor. control switch input pin for turning voltage regulator 1 on/off. input level for this input pin is active ??. control switch input pin for turning voltage regulator 2 on/off. input level for this input pin is active ?? control switch input pin for turning voltage regulator 3 on/off. input level for this input pin is active ??. sense pin of voltage detector 1. output pin of voltage regulator 3. v dd pin. pin no. symbol 2 11 12 13 14 description 5 pins nos. 2, 11, 12, 13 and 14 can be designated as input pins by user's choice. refer to optional mask version guide. pins other than the above 5 pins can be selected from the same pins as those used in r 5ve00 1 (standard ics) to be named by user r 5ve 0
4 optional mask version guide user can designate an optional mask version in accordance with the following optional mask version guide: ? functions of input pins by user ' choice pin no. symbol 2 11 12 13 14 functions control switch of each circuit, sense pin of voltage detector 1 or 2. control switch of each circuit, schmitt trigger input possible. control switch of each circuit only. control switch of each circuit only. control switch of each circuit, sense pin of voltage detector 1 or 2. to be named by user item sense pins of voltage detectors 1, 2 on/off control of regulators and detectors on/off control by toggle input (only pin 11) pins by user's choice output of voltage detectors 1, 2 description ? sense pins of voltage detectors 1, 2 can be connected to output r out 1 , r out 2 , r out 3 , r out 4 of voltage regulators, or v dd . ? on/off control of voltage regulators 1 to 4 and voltage detector 1 can be per - formed by 3 input and gate. ? on/off control of voltage detector 2 can be directly performed. ? on/off control of 4 voltage regulators and 2 voltage detectors can be per - formed by and gate of toggle input and level input. ? edge trigger flip-flop (rise edge operation) is reset and initialized at the rise of power source or at the detection operation of voltage detector 1 or 2. ? flip-flop can be reset by one shot pulse at the detection of voltage detector 1 or 2, or the reset state can be maintained during the detection operation. ? five input pins are available as user's pins as shown in the table shown below. ? on/off control input pins for regulators and detectors. ? sense pins of voltage detectors 1,2. ? active ??input or active ??input can be selected. ? reset output and d out output, which are output from voltage detectors 1, 2, can be set at ??or ??at the time of the detection. ? reset output and d out output, which are output from voltage detectors 1, 2,can be set at ??or ??at the time of off by on/off control. ? output signals of voltage detectors 1, 2 can perform on/off control of voltage regulators 1 to 4. r 5ve 0
5 r 5ve 0 description of ea ch circuit 1. voltage regulators 1,2 ? voltage regulators 1, 2 are linear regulators which can be constructed of external pnp transistor, and are capa - ble of obtaining a large output current by a small dropout voltage. ? output voltage of each of voltage regulators 1, 2 can be set stepwise with a step of 0.1v in the range of 3v to 6v by laser trim. ? voltage regulators 1, 2 can be turned on/off by control pins. ? use external pnp transistor of a low saturation type, with an h fe of 100 or more. ? use voltage regulators 1, 2 with the attachment of a capacitor with a capacitance of 10 f or more to the output pins. 2. voltage regulators 3,4 ? voltage regulators 3, 4 are cmos type linear regulators and have the same structure as those of voltage regulators r 5rl and r 5re series. ? output voltage of each of voltage regulators 3, 4 can be set stepwise with a step of 0.1v in the range of 2v to 6v by laser trim. ? voltage regulators 3, 4 can be turned on/off by control pins. 3. voltage detector 1 ? voltage voltage detector 1 has the same structure as that of voltage detector r 5vl. ? when voltage detector 1 detects the lowering of v sen 1 , the level of the output of voltage detector 1 becomes ? level. the output of voltage detector 1 is nch open drain output. ? voltage detector 1 can be set as follows by optional mask: 1. on/off control of voltage detector 1. 2. output of voltage detector 1 at the detection can be set at ??level or ??level. 3. output of voltage detector 1 at off can be set at ??level or ??level. 4. sense pins of voltage detectors 1, 2 can be connected to output r out 1 , r out 2 , r out 3 , r out 4 of voltage regulators or v dd within the ic. 4. voltage detector 2 ? when voltage detector 2 detects the lowering of v sen 2 , the level of the output of voltage detector 2 becomes ? level. the output of voltage detector 2 is nch open drain output. ? voltage detector 2 can set reset delay time. delay time can be set in accordance with the capacitance c d of external capacitor as shown on the following pages. ? voltage detector 2 can be set as follows by optional mask: 1. on/off control of voltage detector 2. 2. output of voltage detector 2 at the detection can be set at ??level or ??level. 3. output of voltage detector 2 at off can be set at ??level or ??level. 4. sense pins of voltage detectors 2 can be connected to output r out 1 , r out 2 , r out 3 , r out 4 of voltage regulators or v dd within the ic.
6 c u r r e n t s o u r c e e x t e r m a l c a p a c i t o r r d g n d v d d r e s e t v s e n 2 c d v r e f + 5. main power source control (in the case of optional mask version) ?this ic includes built-in edge trigger flip-flop (rise edge operation) and and gate, so that main power source of any instruments can be turned on/off by ?nd?of toggle input and level input. ?edge trigger flip-flop is reset by one shot pulse generator when voltage detector 1 or 2 detects the lowering of the voltage. this flip-flop can be continuously reset during the detection. r 5ve 0 formula for calculating reset delay time is t d = 0.6 9 r d c d wherein r d is the resistance of a built-in resistor and can be set at 1m in ic, so that the above formula is: t d = 0.6 9 10 6 c d voltage detector with delay circuit is constructed as shown below. block diagram of voltage detector with delay circuit.
7 electrical characteristics of r 5ve00 1 symbol item v in input voltage v out output voltage i out output c urrent p d 1 power dissipation1 (16pin ssop (0.8mm pitch)) p d 2 power dissipation2 (16pin ssop (0.65mm pitch)) topt operating temperature range tstg storage temperature range tsolder lead temperature(soldering) rating unit +12 v 0.3 to v in +0.3 v 300 ma 500 mw 470 mw 30 to +80 ?c 40 to +125 ?c 260?c 10s absolute maximum ra tings o verall chara cteristics symbol item v dd operationg voltage range r out 1 , 2 output voltage setting range 1 r out 3 , 4 output voltage setting range 2 v det d etector t hreshold setting range conditions min. typ. max. unit 1.5 10.0 v step of 0.1v 3.0 6.0 v step of 0.1 v 2.0 6.0 v step of 0.1 v 2.0 6.0 v the following three types of ics are available as standard ics.the details of these ics are shown in the section of electrical characteristics on the following pages: list of standard voltage settings type number r 5ve001a r 5ve001b r 5ve001c output voltage of regulator 1 to 4 5.0v 4.0v 3.0v threshold voltage of detector 1 5.4v 4.4v 3.4v threshold voltage of detector 2 4.5v 3.5v 2.5v conditions for input voltage 6.0v 4.8v 3.6v r 5ve 0 absolute maximum ratings are threshold limit values that must not be exceeded even for an instant under any conditions. moreover, such values for any two items must not be reached simultaneously. operation above these absolute maximum ratings may cause degradation or permanent damage to the device. these are stress ratings only and do not necessarily imply functional operation below these limits. absolute maximum ratings
8 r 5ve001a (note 1) unless otherwise provided, v dd = 6.0v, i out = 50ma, co = 10 f, rbe = 100k . (note 2) use external transistor with h fe 3 100. (note 3) quiescent current = operating current of regulators 1, 2 + 0.6/rbe. (note 4) supply current = quiescent (no load) current + load current/h fe . symbol item r out 1 , 2 output voltage i ss 1 , 2 q uiescent c urrent iopr 1 , 2 s upply c urrent v dif 1 , 2 d ropout voltage ? v out load regulation ? i out ? v out line regulation ? v in rr ripple rejection i lim1,2 current limit ? v out o utput v oltage ? topt temperature coefficient conditions min. typ. max. unit 4.875 5.000 5.125 v i out =0ma 100 a i out =80ma 1 ma r out 1 , 2 =5.0v,i out =80ma 0.05 0.3 v r out 1 , 2 =5.0v 1ma i out 80ma 50 mv r out 1 , 2 + 0.3 v v in 10.0v 0.05 0.3 %/v f=120h z ,r ipple 0.5vrms 40 60 db base current of i b 1 , 2 of 1 10 ma pnp t ransistor 100 ppm/?c topt=25?c voltage regulator 3 [ r 5ve001a] symbol item r out 3 output voltage i ss 3 s upply c urrent v dif 3 d ropout voltage ? v out load regulation ? i out ? v out line regulation ? v in i lim 3 current limit ? v out o utput v oltage ? topt temperature coefficient conditions min. typ. max. unit 4.875 5.000 5.125 v 5.0 10.0 a r out 3 =5.0v,i out =50ma 0.3 v r out 3 =5.0v 1ma i out 50ma 50 mv r out 3 + 0.5 v v in 10.0v 0.05 0.3 %/v 100 300 ma 100 ppm/?c topt=25?c voltage regulators 1, 2 [ r 5ve001b] (note) unless otherwise provided, v dd = 6.0v, i out = 30ma r 5ve 0
9 r 5ve 0 voltage regulator 4 [ r 5ve001a] topt=25?c (note) unless otherwise provided, v dd = 6.0v, i out = 10ma voltage detectors 1,2 [ r 5ve001a] symbol item ? det 1 detector threshold 1 ? det 2 detector threshold 2 v hys detector threshold hysteresis i ss 5 i ss 6 supply current i out output current r d output delay resistor i sen s ense pin input current ? v det d etector t hreshold ? topt temperature coefficient conditions min. typ. max. unit voltage detector 1 5.265 5.400 5.535 v voltage detector 2 4.388 4.500 4.612 v ( v det ) 0.05 v voltage detector 1,v dd =6.0v 1.3 3.9 a voltage detector 2,v dd =6.0v 1.5 4.5 a v ds =0.5v, v dd =1.5v 1.5 m a v ds =0.5v, v dd =6.0v 11.6 voltage detector 2 only 0.5 1.0 2.0 m v sen =6.0v 0.5 2 a 100 ppm/?c topt=25?c (note) unless otherwise provided, v dd = 6.0v. symbol item r out 4 output voltage i ss 4 s upply c urrent v dif 4 d ropout voltage ? v out load regulation ? i out ? v out line regulation ? v in i lim 4 current limit ? v out o utput v oltage ? topt temperature coefficient conditions min. typ. max. unit 4.875 5.000 5.125 v 1.3 3.9 a r out 4 =5.0v,i out =20ma 0.3 v r out 4 =5.0v 1ma i out 20ma 50 mv r out 4 + 0.5 v v in 10.0v 0.05 0.3 %/v 100 300 ma 100 ppm/?c
10 input pins [ r 5ve001a] symbol item i leak input leakage current v il control switch low level input voltage v ih control switch high level input voltage v sil s chmitt t rigger low level input voltage v sih s chmitt t rigger high level input voltage v hys s chmitt t rigger hysteresis voltage conditions min. typ. max. unit ? 1 a csw1 to 4 0 0.8 v csw1 to 4 2.4 v dd v optional v optional v optional v topt=25?c (note) unless otherwise provided, v dd = 6.0v. r 5ve 0
11 (note 1) unless otherwise provided, v dd = 4.8v, i out = 50ma, co = 10 f, rbe = 100k . (note 2) use external transistor with h fe 3 100. (note 3) quiescent current = operating current of regulators 1, 2 + 0.6/rbe. (note 4) supply current = quiescent (no load) current + load current/h fe . voltage regulators 1, 2 [ r 5ve001b] (note) unless otherwiseprovided, v dd = 4.8v, i out = 30ma. topt=25?c topt=25?c r 5ve 0 symbol item r out 1 , 2 output voltage i ss 1 , 2 q uiescent c urrent iopr 1 , 2 s upply c urrent v dif 1 , 2 d ropout voltage ? v out load regulation ? i out ? v out line regulation ? v in rr ripple rejection i lim1,2 current limit ? v out o utput v oltage ? topt temperature coefficient conditions min. typ. max. unit 3.900 4.000 4.100 v i out =0ma 100 a i out =80ma 1 ma r out 1 , 2 =4.0v,i out =80ma 0.05 0.3 v r out 1 , 2 =4.0v 1ma i out 80ma 50 mv r out 1 , 2 + 0.3 v v in 10.0v 0.05 0.3 %/v f=120h z ,r ipple 0.5vrms 40 60 db base current of i b 1 , 2 of 1 10 ma pnp t ransistor 100 ppm/?c symbol item r out 3 output voltage i ss 3 s upply c urrent v dif 3 d ropout voltage ? v out load regulation ? i out ? v out line regulation ? v in i lim 3 current limit ? v out o utput v oltage ? topt temperature coefficient conditions min. typ. max. unit 3.900 4.000 4.100 v 5.0 10.0 a r out 3 =4.0v,i out =43ma 0.3 v r out 3 =4.0v 1ma i out 43ma 50 mv r out 3 + 0.5 v v in 10.0v 0.05 0.3 % /v 100 300 ma 100 ppm/?c
12 voltage regulator 4 [ r 5ve001b] topt=25?c (note) unless otherwise provided, v dd = 4.8v, i out = 10ma voltage detectors 1,2 [ r 5ve001b] topt=25?c (note) unless otherwise provided, v dd = 4.8v. r 5ve 0 symbol item r out 4 output voltage i ss 4 s upply c urrent v dif 4 d ropout voltage ? v out load regulation ? i out ? v out line regulation ? v in i lim 4 current limit ? v out o utput v oltage ? topt temperature coefficient conditions min. typ. max. unit 3.900 4.000 4.100 v 1.3 3.9 a r out 4 =4.0v,i out =17.5ma 0.3 v r out 4 =4.0v 1ma i out 17.5ma 50 mv r out 4 + 0.5 v v in 10.0v 0.05 0.3 %/v 100 300 ma 100 ppm/?c symbol item ? det 1 detector threshold 1 ? det 2 detector threshold 2 v hys detector threshold hysteresis i ss 5 i ss 6 supply current i out output current r d output delay resistor i sen s ense pin input current ? v det d etector t hreshold ? topt temperature coefficient conditions min. typ. max. unit voltage detector 1 4.290 4.400 4.510 v voltage detector 2 3.413 3.500 3.587 v (? det ) 0.05 v voltage detector 1,v d d = 4.8v 1.2 3.6 a voltage detector 2,v d d = 4.8v 1.4 4.2 a v d s = 0.5v, v d d =1.5v 1.5 m a v d s = 0.5v, v d d = 4.8v 9.0 voltage detector 2 only 0.5 1.0 2.0 m v se n = 4.8v 0.4 1.6 a 100 ppm/?c
13 input pins [ r 5ve001b] topt=25?c (note) unless otherwise provided, v dd = 4.8v. r 5ve 0 symbol item i leak input leakage current v il control switch low level input voltage v ih control switch high level input voltage v sil s chmitt t rigger low level input voltage v sih s chmitt t rigger high level input voltage v hys s chmitt t rigger hysteresis voltage conditions min. typ. max. unit ? 1 a csw1 to 4 0 0.8 v csw1 to 4 2.0 v dd v optional v optional v optional v
14 (note 1) unless otherwise provided, v dd = 3.6v, i out = 50ma, co = 10 f, rbe = 100k . (note 2) use external transistor with h fe 3 100. (note 3) quiescent current = operating current of regulators 1, 2 + 0.6/rbe. (note 4) supply current = quiescent (no load) current + load current/h fe . voltage regulators 1, 2 [ r 5ve001c] (note) unless otherwise provided, v dd = 3.6v, i out = 30ma topt=25?c topt=25?c r 5ve 0 symbol item r out 1 , 2 output voltage i ss 1 , 2 q uiescent c urrent iopr 1 , 2 s upply c urrent v dif 1 , 2 d ropout voltage ? v out load regulation ? i out ? v out line regulation ? v in rr ripple rejection i lim1,2 current limit ? v out o utput v oltage ? topt temperature coefficient conditions min. typ. max. unit 2.925 3.000 3.075 v i out =0ma 100 a i out =80ma 1 ma r out 1 , 2 =3.0v,i out =80ma 0.05 0.3 v r out 1 , 2 =3.0v 1ma i out 80ma 50 mv r out 1 , 2 + 0.3 v v in 10.0v 0.05 0.3 % /v f=120h z ,r ipple 0.5vrms 40 60 db base current of i b 1 , 2 of 1 10 ma pnp t ransistor 100 ppm/?c symbol item r out 3 output voltage i ss 3 s upply c urrent v dif 3 d ropout voltage ? v out load regulation ? i out ? v out line regulation ? v in i lim 3 current limit ? v out o utput v oltage ? topt temperature coefficient conditions min. typ. max. unit 2.925 3.000 3.075 v 5.0 10.0 a r out 3 =3.0v,i out =35ma 0.3 v r out 3 =3.0v 1ma i out 35ma 50 mv r out 3 + 0.5 v v in 10.0v 0.05 0.3 % /v 100 300 ma 100 ppm/?c
15 voltage regulator 4 [ r 5ve001c] topt=25?c (note) unless otherwise provided, v dd = 3.6v, i out = 10ma voltage detectors 1,2 [ r 5ve001c] topt=25?c (note) unless otherwise provided, v dd = 6.0v. r 5ve 0 symbol item r out 4 output voltage i ss 4 s upply c urrent v dif 4 d ropout voltage ? v out load regulation ? i out ? v out line regulation ? v in i lim 4 current limit ? v out o utput v oltage ? topt temperature coefficient conditions min. typ. max. unit 2.925 3.000 3.075 v 1.1 3.3 a r out 4 =3.0v,i out =15ma 0.3 v r out 4 =3.0v 1ma i out 15ma 50 mv r out 4 + 0.5 v v in 10.0v 0.05 0.3 % /v 100 300 ma 100 ppm/?c symbol item ? det 1 detector threshold 1 ? det 2 detector threshold 2 v hys detector threshold hysteresis i ss 5 i ss 6 supply current i out output current r d output delay resistor i sen s ense pin input current ? v det d etector t hreshold ? topt temperature coefficient conditions min. typ. max. unit voltage detector 1 3.315 3.400 3.485 v voltage detector 2 2.438 2.500 2.562 v (? det ) 0.05 v voltage detector 1,v dd =3.6v 1.1 3.3 a voltage detector 2,v dd =3.6v 1.3 3.9 a v ds =0.5v, v dd =1.5v 1.5 m a v ds =0.5v, v dd =3.6v 6.5 voltage detector 2 only 0.5 1.0 2.0 m v sen =3.6v 0.3 1.2 a 100 ppm/?c
16 input pins [ r 5ve001c] topt=25?c (note) unless otherwise provided, v dd = 3.6v. r 5ve 0 symbol item i leak input leakage current v il control switch low level input voltage v ih control switch high level input voltage v sil s chmitt t rigger low level input voltage v sih s chmitt t rigger high level input voltage v hys s chmitt t rigger hysteresis voltage conditions min. typ. max. unit ? 1 a csw1 to 4 0 0.6 v csw1 to 4 1.6 v dd v optional v optional v optional v
17 regulators 1,2 explana tion of opera tion r o u t 4 i b c 1 , 2 v d d r 2 r 1 g n d c s w 1 , 2 l e v e l s h i f t r o u t 1 , 2 c u r r e n t l i m i t c i r c u i t v r e f + c 1 , 2 each of regulators 1 and 2 is constructed in combination with an external pnp transistor as shown in the above figure. regulators 1 and 2 divide output voltage v out by feed-back registers r1 and r2, and the divid - ed voltage at the node between registers r1 and r2 is compared with the reference voltage by error amplifier, so that the base current of the pnp transistor is adjusted, and a constant voltage is output. the output current from each of regulators 1 and 2 is monitored by current limiter, and when the output current exceeds a limit current, current limiter limits the base current of the pnp transistor to the limit current. the level of input signals to csw 1, 2 is set at the same level as the output voltage level of r out 4 by built-in level shift circuit. phase compensation is made by c 1,2 . regulators 3,4 v r e f c s w 3 r o u t 4 v d d r 2 r 1 g n d a r o u t 3 , 4 c u r r e n t l i m i t c i r c u i t l e v e l s h i f t + regulators 3 and 4 divide output voltage v out by feed-back registers r1 and r2, and the divided voltage at the node between registers r1 and r2 is compared with the reference voltage by error amplifier, so that a con - stant voltage is output. the output current from each of regulators 3 and 4 is monitored by current limiter, and when the output current exceeds a limit current, current limiter limits the output current to the limit current. regulator 4 is short-circuited at point a in the above figure, so that regulator 4 is always in operation. the level of input signals to csw1, 2 is set at the same level as the output voltage level of r out 4 by built-in lev - el shift circuits. r 5ve 0
18 detector 1 v d d c u r r e n t s o u r c e r a r b r c t r . 1 o u t p u t t r . v s e n 1 d o u t g n d n c h v r e f + operation diagram a b r e l e a s e d v o l t a g e + v d e t d e t e c t e d v o l t a g e v d e t m i n i m u m o p e r a t i n g v o l t a g e g n d s t e p g n d o u t p u t v o l t a g e 1 2 3 4 5 d e t e c t o r t h r e s h o l d h y s t e r e s i s step step 1 step 2 step 3 step 4 step 5 comparato r (+ ) pin input voltage i ii ii ii i comparator output h l l l h tr. 1 off on on on off output tr. nch off on indefinite on off i . rb + rc ra + rb + rc ?v dd ii . rb ra + rb ?v dd step 1. output voltage is equal to pull-up voltage. step 2. when input voltage (v sen 1 )reaches the state of vref 3 v sen 1 ?(rb+rc)/(ra+rb+rc)at point a (detected voltag e ? det ), the output of comparator is reversed, so that output voltage becomes gnd. step 3. output voltage becomes indefinite when power source voltage (v dd ) is smaller than minimum operating voltage. when the output is pulled- up,v dd is output. step 4. output voltage becomes equal to gnd. step 5. when input voltage to (v sen 1 ) reaches the state of vref v sen 1 ?rb/(ra + rb) at point b (released voltag e +v det ), the output of comparator is reversed, so that output voltage becomes equal to pulled-up voltage. step of operation the following descriptions deal with v dd pin and v sen 1 pin as connected each other, but detector 1 can be detect - ed the different voltage from v dd through v sen 1 pin. r 5ve 0
19 detector 2 c d c u r r e n t s o u r c e v r e f r a r b r c t r . 1 t r . 2 r b o u t p u t c a p a c i t o r g n d v d d r e s e t v s e n 2 + operation diagram a b m i n i m u m o p e r a t i n g v o l t a g e g n d g n d o u t p u t v o l t a g e s t e p 1 2 3 4 5 d e l a y t i m e d e t e c t o r t h r e s h o l d h y s t e r e s i s r e l e a s e d v o l t a g e + v d e t d e t e c t e d v o l t a g e v d e t i . rb + rc ra + rb + rc ?v dd ii . rb ra + rb ?v dd step 1. output voltage is equal to pull-up voltage. step 2. when input voltage (v sen 2 ) reaches the state of vref 3 v sen 2 ?(rb+rc)/(ra+rb+rc)at point a (detected voltage v det ), the output of compara - tor is reversed, so that output voltage becomes gnd. discharging is performed from c d pin connected to external capacitor. no delay time is generated. step 3. output voltage becomes indefinite when power source voltage (v dd ) is smaller than minimum operating voltage. when the output is pulled- up,v dd is output. step 4. output voltage becomes equal to gnd. step 5. when input voltage (v sen 2 ) reaches the state of vref v sen 2 ?rb/(ra + rb) at point b (released voltage + v det ), the output of comparator is reversed, and the external capacitor is charged through c d pin,so that output voltage becomes equal to pulled-up voltage after a delay timet d (= 0.69 10 6 c d ). step of operation the following descriptions deal with v dd pin and v sen 2 pin as connected each other, but detector 2 can be detect - ed the different voltage from v dd through v sen 2 pin. r 5ve 0 step step 1 step 2 step 3 step 4 step 5 comparato (+) pin input voltage i ii ii ii i comparator output h l l l h tr. 1 off on on on off output tr. nch off on indefinite on off
20 test circuit 1 1 0 0 k w 1 0 0 k w 1 1 6 t r . 1 0 0 k w c d h / l 0 . 1 f 1 0 f 1 0 f 0 . 1 f 1 0 f v d d t r . 8 9 1 0 0 k w h / l h / l t r : 2 s b 8 0 4 ( h f e = 1 5 0 ) i s s csw1 csw2 csw3 regulator 1 h l l regulator 2 l h l regulator 3 l l h regulator 4 l l l detector 1 l l l detector 2 l l l test circuits ( r 5ve001a,b,c) ?output voltage ?current limit (regulator 3, 4) ?quiescent current ?output voltage temperature coefficient ?dropout voltage ?detector threshold ?load regulation ?detector threshold hysteresis ?line regulation ?output voltage transient response test circuit 2 8 9 1 1 6 h / l h / l o p e n 1 0 f 1 0 0 k w t r . 1 0 f 1 0 0 k w t r o p e n o p e n v d d t r : 2 s b 8 0 4 ( h f e = 1 5 0 ) csw1 csw2 regulator 1 h l regulator 2 l h ?ripple rejection (regulator 1, 2) r 5ve 0
21 test circuit 3 o p e n o p e n o p e n h / l h / l i l i m 1 1 1 6 8 9 i l i m 2 v d d a a csw1 csw2 regulator 1 h l regulator 2 l h ?current limit (regulator 1, 2) test circuit 4 o p e n o p e n o p e n 0 . 5 v v d d 1 1 6 8 9 0 . 5 v i o u t 2 i o u t 1 a a ?output current (detector 1, 2) r 5ve 0
22 typical chara cteristics ( r 5ve001a) 1) output voltage vs. input voltage regulator 1,2 (5v) 1 o u t p u t v o l t a g e v o u t ( v ) 2 3 4 5 6 0 2 4 6 8 1 0 1 2 i n p u t v o l t a g e v i n ( v ) i o u t = 5 0 m a 3 0 ? c 2 5 ? c 8 0 ? c i n p u t v o l t a g e v i n ( v ) 1 o u t p u t v o l t a g e v o u t ( v ) 2 3 4 5 6 0 2 4 6 8 1 0 1 2 i o u t = 3 0 m a 3 0 ? c 2 5 ? c 8 0 ? c 1 o u t p u t v o l t a g e v o u t ( v ) 2 3 4 5 6 0 2 4 6 8 1 0 1 2 i n p u t v o l t a g e v i n ( v ) i o u t = 1 0 m a 3 0 ? c 2 5 ? c 8 0 ? c i o u t = 5 0 m a o u t p u t v o l t a g e v o u t ( v ) 4 . 8 4 . 9 5 . 0 5 . 1 4 . 8 5 . 0 5 . 2 5 . 4 5 . 5 2 5 ? c 8 0 ? c i n p u t v o l t a g e v i n ( v ) 3 0 ? c i o u t = 1 0 m a o u t p u t v o l t a g e v o u t ( v ) 4 . 8 4 . 9 5 . 0 5 . 1 4 . 8 5 . 0 5 . 2 5 . 4 5 . 6 i n p u t v o l t a g e v i n ( v ) 3 0 ? c 8 0 ? c 2 5 ? c regulator section regulator 3 (5v) (enlargement) regulator 1,2 (5v) i o u t = 3 0 m a o u t p u t v o l t a g e v o u t ( v ) 4 . 8 4 . 9 5 . 0 5 . 1 4 . 8 5 . 0 5 . 2 5 . 4 5 . 6 i n p u t v o l t a g e v i n ( v ) 3 0 ? c 8 0 ? c 2 5 ? c (enlargement) regulator 3 (5v) (enlargement) regulator 4 (5v) regulator 4 (5v) r 5ve 0
23 2) output voltage vs. output current 3) dropout voltage vs. output curret o u t p u t v o l t a g e v o u t ( v ) v d d = 6 . 0 v 4 . 8 4 . 9 5 . 0 5 . 1 0 1 0 0 2 0 0 3 0 0 o u t p u t c u r r e n t i o u t ( m a ) 8 0 ? c 2 5 ? c 3 0 ? c o u t p u t v o l t a g e v o u t ( v ) 4 . 0 o u t p u t c u r r e n t i o u t ( m a ) 0 4 . 2 4 . 6 4 . 4 4 . 8 5 . 0 5 . 2 5 0 1 0 0 1 5 0 2 0 0 v d d = 6 . 0 v 3 0 ? c 2 5 ? c 8 0 ? c o u t p u t c u r r e n t i o u t ( m a ) 0 1 0 0 2 0 0 3 0 0 d r o p o u t v o l t a g e v d i f ( v ) 0 . 0 0 . 1 0 . 2 0 . 3 2 5 ? c 8 0 ? c 3 0 ? c v d d = 6 . 0 v o u t p u t v o l t a g e v o u t ( v ) o u t p u t c u r r e n t i o u t ( m a ) 0 1 0 0 2 0 0 3 0 0 4 . 0 4 . 2 4 . 4 4 . 6 4 . 8 5 . 0 5 . 2 3 0 ? c 8 0 ? c 2 5 ? c o u t p u t c u r r e n t i o u t ( m a ) 0 1 0 0 2 0 0 3 0 0 d r o p o u t v o l t a g e v d i f ( v ) 0 . 0 0 . 5 1 . 0 1 . 5 2 . 0 3 0 ? c 8 0 ? c 2 5 ? c regulator 1,2 (5v) regulator 3 (5v) regulator 4 (5v) regulator 1,2 (5v) regulator 3 (5v) r 5ve 0
24 4) output voltage vs.temperature d r o p o u t v o l t a g e v d i f ( v ) o u t p u t c u r r e n t i o u t ( m a ) 0 0 . 0 5 0 1 0 0 1 0 0 1 0 0 0 . 5 1 . 0 1 . 5 2 . 0 8 0 ? c 2 5 ? c 3 0 ? c t e m p e r a t u r e t o p t ( ? c ) o u t p u t v o l t a g e v o u t ( v ) 4 0 4 . 9 6 2 0 0 2 0 6 0 8 0 4 . 9 8 5 . 0 0 5 . 0 2 5 . 0 4 ( 5 v ) 4 0 r e g u l a t o r 2 v d d = 6 . 0 v r e g u l a t o r 1 : i o u t = 5 0 m a r e g u l a t o r 2 : i o u t = 5 0 m a r e g u l a t o r 3 : i o u t = 3 0 m a r e g u l a t o r 4 : i o u t = 1 0 m a r e g u l a t o r 3 1 0 0 r e g u l a t o r 1 r e g u l a t o r 4 i o u t = 1 m a c o u t = 4 . 7 f 0 0 1 2 0 1 2 3 4 5 6 7 8 3 4 5 t i m e t ( m s ) i n p u t v o l t a g e / o u t p u t v o l t a g e v i n / v o u t ( v ) i n p u t v o l t a g e o u t p u t v o l t a g e v d d = 6 . 0 v 0 . 5 v r m s r e g u l a t o r 1 , 2 : i o u t = 5 0 m a c = 4 . 7 f r e g u l a t o r 3 : i o u t = 3 0 m a c = 0 . 1 f r e g u l a t o r 4 : i o u t = 1 0 m a c = 0 . 1 f 1 0 1 0 0 1 0 0 0 1 0 0 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 f r e q u e n c y f ( h z ) r i p p l e r e j e c t i o n ( d b ) r e g u l a t o r 1 , 2 r e g u l a t o r 4 r e g u l a t o r 3 regulator 4 (5v) 5) ripple rejection 6) line transient response 1 regulator 1,2 (5v) i o u t = 1 m a c o u t = 0 . 1 f 0 1 2 3 4 5 t i m e t ( m s ) 0 1 2 3 4 5 6 7 8 i n p u t v o l t a g e / o u t p u t v o l t a g e v i n / v o u t ( v ) i n p u t v o l t a g e o u t p u t v o l t a g e regulator 3 (5v) r 5ve 0
25 7) line transient response 2 i o u t = 1 m a c o u t = 0 . 1 f i n p u t v o l t a g e / o u t p u t v o l t a g e v i n / v o u t ( v ) 0 1 2 3 4 5 6 7 8 0 0 1 2 3 4 5 t i m e t ( m s ) i n p u t v o l t a g e o u t p u t v o l t a g e 0 0 1 2 3 4 5 t i m e t ( m s ) i o u t = 1 0 m a c o u t = 4 . 7 f i n p u t v o l t a g e / o u t p u t v o l t a g e v i n / v o u t ( v ) 0 1 2 3 4 5 6 7 8 i n p u t v o l t a g e o u t p u t v o l t a g e i o u t = 1 0 m a c o u t = 0 . 1 f 0 0 1 2 3 4 5 t i m e t ( m s ) i n p u t v o l t a g e / o u t p u t v o l t a g e v i n / v o u t ( v ) 0 1 2 3 4 5 6 7 8 i n p u t v o l t a g e o u t p u t v o l t a g e 0 0 1 2 3 4 5 t i m e t ( m s ) i o u t = 1 0 m a c o u t = 0 . 1 f i n p u t v o l t a g e / o u t p u t v o l t a g e v i n / v o u t ( v ) 0 1 2 3 4 5 6 7 8 i n p u t v o l t a g e o u t p u t v o l t a g e regulator 4 (5v) regulator 4 (5v) regulator 1,2 (5v) regulator 3 (5v) r 5ve 0
26 8) supply current vs. input voltage 9) supply current vs. temperature i n p u t v o l t a g e v d d ( v ) 0 2 4 6 8 1 0 1 2 s u p p l y c u r r e n t i s s ( a ) 0 2 4 6 8 1 0 i n p u t v o l t a g e v d d ( v ) 0 2 4 6 8 1 0 1 2 s u p p l y c u r r e n t i s s ( a ) 0 1 2 3 4 5 s u p p l y c u r r e n t i s s ( a ) 0 2 4 6 8 1 0 t e m p e r a t u r e t o p t ( ? c ) 1 0 0 6 0 4 0 2 0 8 0 0 2 0 4 0 v d d = 6 . 0 v i n p u t v o l t a g e v d d ( v ) 0 2 4 6 8 1 0 1 2 s u p p l y c u r r e n t i s s ( a ) 0 2 4 6 8 1 0 s u p p l y c u r r e n t i s s ( a ) 0 2 4 6 8 1 0 v d d = 6 . 0 v t e m p e r a t u r e t o p t ( ? c ) 1 0 0 6 0 4 0 2 0 8 0 0 2 0 4 0 regulator 1,2 (5v) regulator 3 (5v) regulator 4 (5v) regulator 1,2 (5v) regulator 3 (5v) r 5ve 0
27 10) output voltage transient response for cs w input voltage step v d d = 6 . 0 v t e m p e r a t u r e t o p t ( ? c ) 1 0 0 6 0 4 0 2 0 8 0 2 0 4 0 0 s u p p l y c u r r e n t i s s ( a ) 0 1 2 3 4 5 v d d = 6 . 0 v i o u t = 5 0 m a c o u t = 1 0 f 0 o u t p u t v o l t a g e v o u t ( v ) 1 2 7 6 5 4 3 t i m e t ( s ) 0 1 0 0 2 0 0 3 0 0 v d d = 6 . 0 v i o u t = 1 0 m a c o u t = 0 . 1 f 0 o u t p u t v o l t a g e v o u t ( v ) 1 2 7 6 5 4 3 t i m e t ( s ) 0 4 0 0 8 0 0 1 2 0 0 v d d = 6 . 0 v i o u t = 3 0 m a c o u t = 0 . 1 f 0 o u t p u t v o l t a g e v o u t ( v ) 1 2 7 6 5 4 3 t i m e t ( s ) 0 2 0 0 4 0 0 6 0 0 regulator 4 (5v) regulator 4 (5v) regulator 1,2 (5v) regulator 3 (5v) r 5ve 0 (note) control switch becomes on ( ??) at 0 s.
28 1) output voltage vs. input voltage detector 1,2 8 0 ? c 2 5 ? c 0 . 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 0 . 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 4 . 0 3 . 5 i n p u t v o l t a g e v d d ( v ) o u t p u t v o l t a g e v o u t ( v ) v d e t 1 , 2 = 2 . 0 v 3 0 ? c 2 5 ? c i n p u t v o l t a g e v d d ( v ) 0 2 4 6 8 1 0 1 2 0 2 4 1 3 s u p p l y c u r r e n t i s s ( a ) 8 0 ? c 3 0 ? c 5 . 7 5 . 6 5 . 5 5 . 4 5 . 3 t e m p e r a t u r e t o p t ( ? c ) 1 0 0 6 0 4 0 2 0 8 0 0 2 0 4 0 d e t e c t e d / r e l e a s e d v o l t a g e v d e t ( v ) v d e t 1 + v d e t 1 8 0 ? c 2 5 ? c 3 0 ? c v d s = 0 . 5 v 0 0 4 8 1 2 1 6 2 0 2 4 1 2 3 4 5 6 7 o u t p u t c u r r e n t i o u t ( v ) i n p u t v o l t a g e v d d ( v ) 4 . 8 4 . 7 4 . 6 4 . 5 4 . 4 t e m p e r a t u r e t o p t ( ? c ) 1 0 0 6 0 4 0 2 0 8 0 0 2 0 4 0 d e t e c t e d / r e l e a s e d v o l t a g e v d e t ( v ) v d e t 2 + v d e t 2 detector section detector 1 detector 1,2 0 4 1 0 2 6 s u p p l y c u r r e n t i s s ( a ) i n p u t v o l t a g e v d d ( v ) 0 2 4 6 8 1 0 1 2 8 8 0 ? c 2 5 ? c 3 0 ? c detector 2 3) supply current vs. input voltage 2) output current vs. input voltage 4) detected/released voltage vs. temperature detector 1 detector 2 r 5ve 0
29 5) output delay time (fall) vs. load capacitance detector 1,2 t o p t = 2 5 ? c d e t e c t o r 2 l o a d c a p a c i t a n c e c o u t ( f ) o u t p u t d e l a y t i m e t p h l ( s ) 1 0 - 3 1 0 - 7 1 0 - 9 1 0 - 8 1 0 - 6 1 0 - 4 1 0 - 5 1 0 - 6 d e t e c t o r 2 d e t e c t o r 1 c d = d e t a c h v d d = 3 . 0 v t o p t = 2 5 ? c c o u t = d e t a c h c d p i n e x t e r n a l c a p a c i t a n c e c d ( f ) o u t p u t d e l a y t i m e t p h l ( s ) 1 0 - 5 1 0 - 6 1 0 - 9 1 0 - 8 1 0 - 7 1 0 - 6 t o p t = 2 5 ? c c o u t = d e t a c h c d = d e t a c h i n p u t v o l t a g e v d d ( v ) o u t p u t d e l a y t i m e t p l h ( s ) 0 2 4 1 0 8 6 1 0 - 3 1 0 - 4 1 0 - 5 d e t e c t o r 2 d e t e c t o r 1 detector 1 detector 1,2 t o p t = 2 5 ? c o u t p u t d e l a y t i m e t p l h ( s ) c d p i n e x t e r n a l c a p a c i t a n c e c d ( f ) 1 0 - 0 1 0 - 1 1 0 - 2 1 0 - 3 1 0 - 9 1 0 - 8 1 0 - 7 1 0 - 6 detector 2 7) output delay time (fall) vs. c d pin external capacitance 6) output delay time (rise) vs. input voltage 8) output delay time (rise) vs. c d pin external capacitance r 5ve 0
30 1) output voltage vs. input voltage regulator 1,2 (4v) 1 o u t p u t v o l t a g e v o u t ( v ) 2 3 4 5 0 2 4 6 8 1 0 1 2 i n p u t v o l t a g e v i n ( v ) i o u t = 5 0 m a 3 0 ? c 8 0 ? c 2 5 ? c i o u t = 3 0 m a 0 2 4 6 8 1 0 1 2 i n p u t v o l t a g e v i n ( v ) 1 o u t p u t v o l t a g e v o u t ( v ) 2 3 4 5 3 0 ? c 8 0 ? c 2 5 ? c i o u t = 1 0 m a 1 o u t p u t v o l t a g e v o u t ( v ) 2 3 4 5 0 2 4 6 8 1 0 1 2 i n p u t v o l t a g e v i n ( v ) 3 0 ? c 2 5 ? c 8 0 ? c 3 . 8 4 . 0 4 . 2 4 . 4 4 . 6 i n p u t v o l t a g e v i n ( v ) 3 . 8 4 . 0 3 . 9 4 . 1 o u t p u t v o l t a g e v o u t ( v ) i o u t = 5 0 m a 3 0 ? c 2 5 ? c 8 0 ? c i o u t = 1 0 m a 3 . 8 4 . 0 3 . 9 4 . 1 o u t p u t v o l t a g e v o u t ( v ) 3 . 8 4 . 0 4 . 2 4 . 4 4 . 6 i n p u t v o l t a g e v i n ( v ) 4 3 0 ? c 2 5 ? c 8 0 ? c regulator section regulator 3 (4v) (enlargement) regulator 1,2 (4v) i o u t = 3 0 m a 3 . 8 4 . 0 3 . 9 4 . 1 o u t p u t v o l t a g e v o u t ( v ) 3 . 8 4 . 0 4 . 2 4 . 4 4 . 6 i n p u t v o l t a g e v i n ( v ) 3 0 ? c 8 0 ? c 2 5 ? c (enlargement) regulator 3 (4v) (enlargement) regulator 4 (4v) regulator 4 (4v) r 5ve 0
31 2) output voltage vs. output current 3) dropout voltage vs. output curret v d d = 4 . 8 v o u t p u t v o l t a g e v o u t ( v ) 3 . 8 3 . 9 4 . 0 4 . 1 0 1 0 0 2 0 0 3 0 0 o u t p u t c u r r e n t i o u t ( m a ) 3 0 ? c 2 5 ? c 8 0 ? c v d d = 4 . 8 v o u t p u t v o l t a g e v o u t ( v ) o u t p u t c u r r e n t i o u t ( m a ) 0 5 0 1 0 0 1 5 0 3 . 0 3 . 2 3 . 4 3 . 6 3 . 8 4 . 0 4 . 2 3 0 ? c 2 5 ? c 8 0 ? c o u t p u t c u r r e n t i o u t ( m a ) 0 1 0 0 2 0 0 3 0 0 d r o p o u t v o l t a g e v d i f ( v ) 0 . 0 0 . 1 0 . 2 0 . 3 8 0 ? c 2 5 ? c 3 0 ? c v d d = 4 . 8 v o u t p u t v o l t a g e v o u t ( v ) o u t p u t c u r r e n t i o u t ( m a ) 0 1 0 0 2 0 0 3 0 0 3 . 0 3 . 2 3 . 4 3 . 6 3 . 8 4 . 0 4 . 2 3 0 ? c 2 5 ? c 8 0 ? c o u t p u t c u r r e n t i o u t ( m a ) 0 1 0 0 2 0 0 3 0 0 d r o p o u t v o l t a g e v d i f ( v ) 0 . 0 0 . 2 0 . 8 1 . 4 2 . 0 1 . 8 1 . 6 1 . 2 1 . 0 0 . 6 0 . 4 8 0 ? c 2 5 ? c 3 0 ? c regulator 1,2 (4v) regulator 3 (4v) regulator 4 (4v) regulator 1,2 (4v) regulator 3 (4v) r 5ve 0
32 4) output voltage vs.temperature o u t p u t c u r r e n t i o u t ( m a ) 0 2 0 4 0 6 0 1 0 0 d r o p o u t v o l t a g e v d i f ( v ) 0 . 0 0 . 5 1 . 0 1 . 5 2 . 0 8 0 2 5 ? c 8 0 ? c 3 0 ? c ( 4 v ) o u t p u t v o l t a g e v o u t ( v ) 3 . 9 6 3 . 9 8 4 . 0 0 4 . 0 2 4 . 0 4 4 0 t e m p e r a t u r e t o p t ( ? c ) 2 0 0 2 0 6 0 8 0 4 0 1 0 0 v d d = 4 . 8 v r e g u l a t o r 1 : i o u t = 5 0 m a r e g u l a t o r 2 : i o u t = 5 0 m a r e g u l a t o r 3 : i o u t = 3 0 m a r e g u l a t o r 4 : i o u t = 1 0 m a r e g u l a t o r 2 r e g u l a t o r 1 r e g u l a t o r 3 r e g u l a t o r 4 0 0 1 2 3 4 5 t i m e t ( m s ) 0 1 2 3 4 5 6 7 8 i n p u t v o l t a g e / o u t p u t v o l t a g e v i n / v o u t ( v ) i o u t = 1 m a c o u t = 4 . 7 f i n p u t v o l t a g e o u t p u t v o l t a g e v d d = 4 . 8 v 0 . 5 v r m s r e g u l a t o r 1 , 2 : i o u t = 5 0 m a c = 4 . 7 f r e g u l a t o r 3 : i o u t = 3 0 m a c = 0 . 1 f r e g u l a t o r 4 : i o u t = 1 0 m a c = 0 . 1 f 1 0 1 0 0 1 0 0 0 1 0 0 0 0 f r e q u e n c y f ( h z ) 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 r i p p l e r e j e c t i o n ( d b ) r e g u l a t o r 3 r e g u l a t o r 4 r e g u l a t o r 1 , 2 regulator 4 (4v) 5) ripple rejection 6) linet transient response 1 regulator 1,2 (4v) i o u t = 1 m a c o u t = 0 . 1 f 0 0 1 2 3 4 5 t i m e t ( m s ) 0 1 2 3 4 5 6 7 8 i n p u t v o l t a g e / o u t p u t v o l t a g e v i n / v o u t ( v ) i n p u t v o l t a g e o u t p u t v o l t a g e regulator 3 (4v) r 5ve 0
33 7) line transient response 2 i o u t = 1 m a c o u t = 0 . 1 f 0 0 1 2 3 4 5 t i m e t ( m s ) i n p u t v o l t a g e / o u t p u t v o l t a g e v i n / v o u t ( v ) 0 1 2 3 4 5 6 7 8 i n p u t v o l t a g e o u t p u t v o l t a g e 0 0 1 2 3 4 5 t i m e t ( m s ) i n p u t v o l t a g e / o u t p u t v o l t a g e v i n / v o u t ( v ) 0 1 2 3 4 5 6 7 8 i o u t = 1 0 m a c o u t = 4 . 7 f i n p u t v o l t a g e o u t p u t v o l t a g e 0 0 1 2 3 4 5 t i m e t ( m s ) i n p u t v o l t a g e / o u t p u t v o l t a g e v i n / v o u t ( v ) 0 1 2 3 4 5 6 7 8 i o u t = 1 0 m a c o u t = 0 . 1 f i n p u t v o l t a g e o u t p u t v o l t a g e 0 0 1 2 3 4 5 t i m e t ( m s ) i n p u t v o l t a g e / o u t p u t v o l t a g e v i n / v o u t ( v ) 0 1 2 3 4 5 6 7 8 i o u t = 1 0 m a c o u t = 0 . 1 f i n p u t v o l t a g e o u t p u t v o l t a g e regulator 4 (4v) regulator 4 (4v) regulator 1,2 (4v) regulator 3 (4v) r 5ve 0
34 8) supply current vs. input voltage 9) supply current vs. temperature s u p p l y c u r r e n t i s s ( a ) 0 2 4 6 8 1 0 i n p u t v o l t a g e v d d ( v ) 0 2 4 6 8 1 0 1 2 i n p u t v o l t a g e v d d ( v ) 0 2 4 6 8 1 0 1 2 s u p p l y c u r r e n t i s s ( a ) 0 1 2 3 4 5 v d d = 4 . 8 v t e m p e r a t u r e t o p t ( ? c ) 1 0 0 6 0 4 0 2 0 8 0 0 2 0 4 0 s u p p l y c u r r e n t i s s ( a ) 0 2 4 6 8 1 0 i n p u t v o l t a g e v d d ( v ) 0 2 4 6 8 1 0 1 2 s u p p l y c u r r e n t i s s ( a ) 0 2 4 6 8 1 0 v d d = 4 . 8 v t e m p e r a t u r e t o p t ( ? c ) 1 0 0 6 0 4 0 2 0 8 0 0 2 0 4 0 s u p p l y c u r r e n t i s s ( a ) 0 2 4 6 8 1 0 regulator 1,2 (4v) regulator 3 (4v) regulator 4 (4v) regulator 1,2 (4v) regulator 3 (4v) r 5ve 0
35 10) output voltage transient response for cs w input voltage step v d d = 4 . 8 v t e m p e r a t u r e t o p t ( ? c ) 1 0 0 6 0 4 0 2 0 8 0 0 2 0 4 0 s u p p l y c u r r e n t i s s ( a ) 0 1 2 3 4 5 v d d = 4 . 8 v i o u t = 5 0 m a c o u t = 1 0 f 0 o u t p u t v o l t a g e v o u t ( v ) 1 2 7 6 5 4 3 t i m e t ( s ) 0 1 0 0 2 0 0 3 0 0 v d d = 4 . 8 v i o u t = 1 0 m a c o u t = 0 . 1 f t i m e t ( s ) 0 4 0 0 8 0 0 1 2 0 0 0 o u t p u t v o l t a g e v o u t ( v ) 1 2 7 6 5 4 3 v d d = 4 . 8 v i o u t = 3 0 m a c o u t = 0 . 1 f t i m e t ( s ) 0 2 0 0 4 0 0 6 0 0 0 o u t p u t v o l t a g e v o u t [ v ] 1 2 7 6 5 4 3 regulator 4 (4v) regulator 4 (4v) regulator 1,2 (4v) regulator 3 (4v) r 5ve 0 (note) control switch becomes on ( ??) at 0 s.
36 1) output voltage vs. input voltage detector 1,2 v d e t 1 , 2 = 2 . 0 v 8 0 ? c 2 5 ? c 3 0 ? c 0 . 0 4 . 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 o u t p u t v o l t a g e v o u t ( v ) 0 . 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 i n p u t v o l t a g e v d d ( v ) 8 0 ? c 2 5 ? c 3 0 ? c 0 2 4 1 3 s u p p l y c u r r e n t i s s ( a ) i n p u t v o l t a g e v d d ( v ) 0 2 4 6 8 1 0 1 2 t e m p e r a t u r e t o p t ( ? c ) 1 0 0 6 0 4 0 2 0 8 0 0 2 0 4 0 4 . 7 4 . 6 4 . 5 4 . 4 4 . 3 d e t e c t e d / r e l e a s e d v o l t a g e v d e t ( v ) v d e t 1 + v d e t 1 v d s = 0 . 5 v 3 0 ? c 0 1 2 3 4 5 6 7 i n p u t v o l t a g e v d d ( v ) 0 4 8 1 2 1 6 2 0 2 4 o u t p u t v o l t a g e v o u t ( v ) 2 5 ? c 8 0 ? c t e m p e r a t u r e t o p t ( ? c ) 1 0 0 6 0 4 0 2 0 8 0 0 2 0 4 0 3 . 8 3 . 7 3 . 6 3 . 5 3 . 4 d e t e c t e d / r e l e a s e d v o l t a g e v d e t ( v ) v d e t 2 + v d e t 2 detector section detector 1 detector 1,2 8 0 ? c 2 5 ? c 3 0 ? c 0 4 1 0 2 6 s u p p l y c u r r e n t i s s ( a ) 8 i n p u t v o l t a g e v d d ( v ) 0 2 4 6 8 1 0 1 2 detector 2 3) supply current vs. input voltage 2) output current vs. input voltage 4) detected/released voltage vs. temperature detector 1 detector 2 r 5ve 0
37 5) output delay time (fall) vs. load capacitance detector 1,2 t o p t = 2 5 ? c d e t e c t o r 2 o u t p u t d e l a y t i m e t p h l ( s ) 1 0 - 3 l o a d c a p a c i t a n c e c o u t ( f ) d e t e c t o r 1 d e t e c t o r 2 1 0 - 6 1 0 - 7 1 0 - 9 1 0 - 8 1 0 - 5 1 0 - 6 1 0 - 4 c d = d e t a c h v d d = 3 . 0 v t o p t = 2 5 ? c c o u t = d e t a c h o u t p u t d e l a y t i m e t p h l ( s ) 1 0 - 9 1 0 - 8 1 0 - 7 1 0 - 6 1 0 - 5 1 0 - 6 c d p i n e x t e r n a l c a p a c i t a n c e c d ( f ) t o p t = 2 5 ? c c o u t = d e t a c h c d = d e t a c h i n p u t v o l t a g e v d d ( v ) 0 2 4 1 0 8 6 d e t e c t o r 2 d e t e c t o r 1 1 0 - 3 1 0 - 4 1 0 - 5 o u t p u t d e l a y t i m e t p l h ( s ) detector 2 detector 1,2 t o p t = 2 5 ? c o u t p u t d e l a y t i m e t p l h ( s ) 1 0 - 1 1 0 - 0 1 0 - 2 1 0 - 3 1 0 - 9 1 0 - 8 1 0 - 6 1 0 - 7 c d p i n e x t e r n a l c a p a c i t a n c e c d ( f ) detector 2 7) output delay time (fall) vs. c d pin external capacitance 6) output delay time (rise) vs. input voltage 8) output delay time (rise) vs. c d pin external capacitance r 5ve 0
38 1) output voltage vs. input voltage regulator 1,2 (3v) 0 2 4 6 8 1 0 1 2 i n p u t v o l t a g e v i n ( v ) i o u t = 5 0 m a 2 . 2 o u t p u t v o l t a g e v o u t ( v ) 2 . 4 2 . 6 2 . 8 3 . 0 2 . 0 1 . 8 3 . 2 8 0 ? c 2 5 ? c 3 0 ? c 1 . 5 o u t p u t v o l t a g e v o u t ( v ) 2 . 0 2 . 5 3 . 0 3 . 5 0 2 4 6 8 1 0 1 2 i n p u t v o l t a g e v i n ( v ) i o u t = 3 0 m a 3 0 ? c 8 0 ? c 2 5 ? c o u t p u t v o l t a g e v o u t ( v ) 1 . 5 2 . 0 2 . 5 3 . 0 i o u t = 1 0 m a 3 0 ? c 2 5 ? c 8 0 ? c 0 2 4 6 8 1 0 1 2 i n p u t v o l t a g e v i n ( v ) 8 0 ? c i o u t = 5 0 m a 2 . 8 3 . 0 3 . 2 3 . 4 3 . 6 i n p u t v o l t a g e v i n ( v ) 2 . 6 2 . 8 3 . 0 2 . 9 3 . 1 o u t p u t v o l t a g e v o u t ( v ) 3 0 ? c 2 5 ? c 3 0 ? c 2 5 ? c 8 0 ? c i o u t = 1 0 m a 2 . 8 3 . 0 2 . 9 3 . 1 o u t p u t v o l t a g e v o u t ( v ) 2 . 8 3 . 0 3 . 2 3 . 4 3 . 6 i n p u t v o l t a g e v i n ( v ) regulator section regulator 3 (3v) (enlargement) regulator 1,2 (3v) 3 0 ? c 2 5 ? c 8 0 ? c 2 . 8 3 . 0 3 . 2 3 . 4 3 . 6 i n p u t v o l t a g e v i n ( v ) 2 . 8 3 . 0 2 . 9 3 . 1 o u t p u t v o l t a g e v o u t ( v ) i o u t = 3 0 m a (enlargement) regulator 3 (3v) (enlargement) regulator 4 (3v) regulator 4 (3v) r 5ve 0
39 2) output voltage vs. output current 3) dropout voltage vs. output current v d d = 3 . 6 v o u t p u t v o l t a g e v o u t ( v ) 2 . 8 2 . 9 3 . 0 3 . 1 0 1 0 0 2 0 0 3 0 0 o u t p u t c u r r e n t i o u t ( m a ) 8 0 ? c 3 0 ? c 2 5 ? c o u t p u t c u r r e n t i o u t ( m a ) 0 5 0 1 0 0 1 5 0 v d d = 3 . 6 v 2 5 ? c o u t p u t v o l t a g e v o u t ( v ) 2 . 0 2 . 2 2 . 4 2 . 6 2 . 8 3 . 0 3 . 2 8 0 ? c 3 0 ? c 2 5 ? c 8 0 ? c 3 0 ? c 0 1 0 0 2 0 0 3 0 0 o u t p u t c u r r e n t i o u t ( m a ) d r o p o u t v o l t a g e v o u t ( v ) 0 . 0 0 . 1 0 . 2 0 . 3 o u t p u t v o l t a g e v o u t ( v ) 2 . 0 2 . 2 2 . 6 2 . 4 2 . 8 3 . 0 v d d = 3 . 6 v 3 0 ? c 2 5 ? c 8 0 ? c 0 1 0 0 2 0 0 3 0 0 o u t p u t c u r r e n t i o u t ( m a ) o u t p u t c u r r e n t i o u t ( m a ) 0 1 0 0 2 0 0 3 0 0 d r o p o u t v o l t a g e v d i f ( v ) 0 . 0 0 . 5 1 . 0 1 . 5 2 . 0 8 0 ? c 3 0 ? c 2 5 ? c regulator 1,2 (3v) regulator 3 (3v) regulator 4 (3v) regulator 1,2 (3v) regulator 3 (3v) r 5ve 0
40 4) output voltage vs.temperature d r o p o u t v o l t a g e v d i f ( v ) 0 . 0 0 . 5 1 . 0 1 . 5 2 . 0 8 0 ? c 2 5 ? c 3 0 ? c o u t p u t c u r r e n t i o u t ( m a ) 0 2 0 4 0 6 0 1 0 0 8 0 t e m p e r a t u r e t o p t ( ? c ) 4 0 2 0 0 2 0 4 0 6 0 8 0 1 0 0 2 . 9 6 o u t p u t v o l t a g e v o u t ( v ) 2 . 9 7 2 . 9 8 2 . 9 9 3 . 0 0 3 . 0 1 3 . 0 2 v d d = 3 . 6 v r e g u l a t o r 1 : i o u t = 5 0 m a r e g u l a t o r 2 : i o u t = 5 0 m a r e g u l a t o r 3 : i o u t = 3 0 m a r e g u l a t o r 4 : i o u t = 1 0 m a r e g u l a t o r 3 r e g u l a t o r 1 r e g u l a t o r 4 r e g u l a t o r 2 0 1 2 3 4 5 t i m e t ( m s ) 0 1 2 3 4 5 6 7 8 i n p u t v o l t a g e / o u t p u t v o l t a g e v i n / v o u t ( v ) i o u t = 1 m a c o u t = 4 . 7 f i n p u t v o l t a g e o u t p u t v o l t a g e 1 0 1 0 0 1 0 0 0 1 0 0 0 0 f r e q u e n c y f ( h z ) 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 r i p p l e r e j e c t i o n ( d b ) r e g u l a t o r 1 , 2 r e g u l a t o r 3 r e g u l a t o r 4 v d d = 3 . 6 v 0 . 5 v r m s r e g u l a t o r 1 , 2 : i o u t = 5 0 m a c = 4 . 7 f r e g u l a t o r 3 : i o u t = 3 0 m a c = 0 . 1 f r e g u l a t o r 4 : i o u t = 1 0 m a c = 0 . 1 f regulator 4 (3v) 5) ripple rejection 6) line transient response 1 regulator 1,2 (3v) i o u t = 1 m a c o u t = 0 . 1 f 0 1 2 3 4 5 t i m e t ( m s ) 0 1 2 3 4 5 6 7 8 i n p u t v o l t a g e / o u t p u t v o l t a g e v i n / v o u t ( v ) i n p u t v o l t a g e o u t p u t v o l t a g e regulator 3 (3v) r 5ve 0
41 7) line transient response 2 i o u t = 1 m a c o u t = 0 . 1 f i n p u t v o l t a g e / o u t p u t v o l t a g e v i n / v o u t ( v ) 0 1 2 3 4 5 6 7 8 0 0 1 2 3 4 5 t i m e t ( m s ) i n p u t v o l t a g e o u t p u t v o l t a g e i o u t = 1 0 m a c o u t = 4 . 7 f i n p u t v o l t a g e / o u t p u t v o l t a g e v i n / v o u t ( v ) 0 1 2 3 4 5 6 7 8 0 0 1 2 3 4 5 t i m e t ( m s ) i n p u t v o l t a g e o u t p u t v o l t a g e i o u t = 1 0 m a c o u t = 0 . 1 f 0 0 1 2 3 4 5 t i m e t ( m s ) i n p u t v o l t a g e / o u t p u t v o l t a g e v i n / v o u t ( v ) 0 1 2 3 4 5 6 7 8 i n p u t v o l t a g e o u t p u t v o l t a g e i o u t = 1 0 m a c o u t = 0 . 1 f 0 0 1 2 3 4 5 t i m e t ( m s ) i n p u t v o l t a g e / o u t p u t v o l t a g e v i n / v o u t ( v ) 0 1 2 3 4 5 6 7 8 i n p u t v o l t a g e o u t p u t v o l t a g e regulator 4 (3v) regulator 4 (3v) regulator 1,2 (3v) regulator 3 (3v) r 5ve 0
42 8) supply current vs. input voltage 9) supply current vs. temperature s u p p l y c u r r e n t i s s ( a ) 0 2 4 6 8 1 0 i n p u t v o l t a g e v d d ( v ) 0 2 4 6 8 1 0 1 2 s u p p l y c u r r e n t i s s ( a ) 0 1 2 3 4 5 i n p u t v o l t a g e v d d ( v ) 0 2 4 6 8 1 0 1 2 v d d = 3 . 6 v t e m p e r a t u r e t o p t ( ? c ) 1 0 0 6 0 4 0 2 0 8 0 0 2 0 4 0 s u p p l y c u r r e n t i s s ( a ) 0 2 4 6 8 1 0 s u p p l y c u r r e n t i s s ( a ) 0 2 4 6 8 1 0 i n p u t v o l t a g e v d d ( v ) 0 2 4 6 8 1 0 1 2 v d d = 3 . 6 v t e m p e r a t u r e t o p t ( ? c ) 1 0 0 6 0 4 0 2 0 8 0 0 2 0 4 0 s u p p l y c u r r e n t i s s ( a ) 0 2 4 6 8 1 0 regulator 1,2 (3v) regulator 3 (3v) regulator 4 (3v) regulator 1,2 (3v) regulator 3 (3v) r 5ve 0
43 10) output voltage transient response for cs w input voltage step s u p p l y c u r r e n t i s s ( a ) 0 1 2 3 4 5 t e m p e r a t u r e t o p t ( ? c ) 1 0 0 6 0 4 0 2 0 8 0 2 0 4 0 0 v d d = 3 . 6 v v d d = 3 . 6 v i o u t = 5 0 m a c o u t = 1 0 f t i m e t ( s ) 0 1 0 0 2 0 0 3 0 0 0 o u t p u t v o l t a g e v o u t ( v ) 1 2 7 6 5 4 3 v d d = 3 . 6 v i o u t = 1 0 m a c o u t = 0 . 1 f t i m e t ( s ) 0 4 0 0 8 0 0 1 2 0 0 0 o u t p u t v o l t a g e v o u t ( v ) 1 2 7 6 5 4 3 t i m e t ( s ) 0 2 0 0 4 0 0 6 0 0 0 o u t p u t v o l t a g e v o u t ( v ) 1 2 7 6 5 4 3 v d d = 3 . 6 v i o u t = 3 0 m a c o u t = 0 . 1 f regulator 4 (3v) regulator 4 (3v) regulator 1,2 (3v) regulator 3 (3v) r 5ve 0 (note) control switch becomes on ( ??) at 0 s.
44 1) output voltage vs. input voltage detector 1,2 v d e t 1 , 2 = 2 . 0 v 8 0 ? c 2 5 ? c 3 0 ? c 0 . 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 4 . 0 3 . 5 o u t p u t v o l t a g e v o u t ( v ) 0 . 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 i n p u t v o l t a g e v d d ( v ) 0 2 4 1 3 s u p p l y c u r r e n t i s s ( a ) i n p u t v o l t a g e v d d ( v ) 0 2 4 6 8 1 0 1 2 2 5 ? c 8 0 ? c 3 0 ? c 3 . 7 3 . 6 3 . 5 3 . 4 3 . 3 d e t e c t e d / r e l e a s e d v o l t a g e v d e t ( v ) t e m p e r a t u r e t o p t ( ? c ) 1 0 0 6 0 4 0 2 0 8 0 0 2 0 4 0 + v d e t 1 v d e t 1 0 1 2 3 4 5 6 7 i n p u t v o l t a g e v d d ( v ) 2 5 ? c 8 0 ? c 3 0 ? c v s d = 0 . 5 v 0 4 8 1 2 1 6 2 0 2 4 o u t p u t c u r r e n t i o u t ( m a ) 2 . 8 2 . 7 2 . 6 2 . 5 2 . 4 d e t e c t e d / r e l e a s e d v o l t a g e v d e t ( v ) t e m p e r a t u r e t o p t ( ? c ) 1 0 0 6 0 4 0 2 0 8 0 0 2 0 4 0 + v d e t 2 v d e t 2 detector section detector 1 detector 1,2 0 4 1 0 2 6 s u p p l y c u r r e n t i s s ( a ) 8 i n p u t v o l t a g e v d d ( v ) 0 2 4 6 8 1 0 1 2 8 0 ? c 2 5 ? c 3 0 ? c detector 2 3) supply current vs. input voltage 2) output current vs. input voltage 4) detected/released voltage vs. temperature detector 1 detector 2 r 5ve 0
45 5) output delay time (fall) vs. load capacitance detector 1,2 1 0 - 6 d e t e c t o r 1 d e t e c t o r 2 l o a d c a p a c i t a n c e c o u t ( f ) o u t p u t d e l a y t i m e t p h l ( s ) 1 0 - 3 1 0 - 5 1 0 - 6 1 0 - 7 1 0 - 9 1 0 - 8 1 0 - 4 t o p t = 2 5 ? c d e t e c t o r 2 c d = d e t a c h v d d = 3 . 0 v t o p t = 2 5 ? c c o u t = d e t a c h c d p i n e x t e r n a l c a p a c i t a n c e c d ( f ) o u t p u t d e l a y t i m e t p h l ( s ) 1 0 - 9 1 0 - 8 1 0 - 5 1 0 - 6 1 0 - 6 1 0 - 7 t o p t = 2 5 ? c c o u t = d e t a c h c d = d e t a c h i n p u t v o l t a g e v d d ( v ) o u t p u t d e l a y t i m e t p l h ( s ) 0 2 4 1 0 8 6 1 0 - 3 1 0 - 4 1 0 - 5 d e t e c t o r 2 d e t e c t o r 1 detector 2 detector 1,2 o u t p u t d e l a y t i m e t p l h ( s ) 1 0 - 1 1 0 - 0 1 0 - 2 1 0 - 3 c d p i n e x t e r n a l c a p a c i t a n c e c d ( f ) 1 0 - 9 1 0 - 8 1 0 - 6 1 0 - 7 t o p t = 2 5 ? c detector 2 7) output delay time (fall) vs. c d pin external capacitance 6) output delay time (rise) vs. input voltage 8) output delay time (rise) vs. c d pin external capacitance r 5ve 0
46 typical applica tion r 5ve 0 in this example of the circuit, the output of regulator 4 is used as the power source for cpu. the voltage input to csw 1, 2, 3 pins is subject to level shift within the ic so as to have the same level as that of the voltage of cpu. therefore csw 1, 2, 3 pins can be directly connected to cpu. detector 1 monitors the voltage of the battery and detector 2 monitors the voltage of the power source for cpu. v c c c 5 c 1 c 2 c 4 c 3 c d t r r 1 r 2 r 3 r 4 t r v d d r o u t 4 v s e n 2 c d r e s e t d o u t r o u t 1 i b c 1 g n d r o u t 3 v s e n 1 c s w 3 c s w 1 r o u t 2 i b c 2 i / o l o g i c u n i t c p u i n t r e s e t m e m o r y u n i t t r a n s m i t t e r u n i t r e c e i v e r / a u d i o u n i t s b d c s w 2 i / o i / o r 5 v e 0 0 1 c1,2,5=10 f / c3,4=0.1 f / c d =0.1 f r1,2,3,4=100k tr:2sb799(nec pnp type,h fe =100 to 200) sbd:ma717(panasonic) applica tion hints when using these ics, be sure to take care of the following points : minimize the impedance of v dd and gnd wiring. in particular, with respect to the v dd wiring, the output cur - rent of regulators flows thereinto, so that when the wiring impedance is high, the operation of the ic tends to be unstable and is vulnerable to noise. provide a capacitor with a capacitance of about 10 f between v dd pin and gnd pin with a minimum wiring length. rush current flows into the capacitor connected to the output of regulators at the start of the operation of the regulators. in particular, regulators 1, 2 are equipped with external pnp transistor and accordingly have excellent drive performance. therefore, when regulators 1, 2 start to operate, for example, under the conditions that h fe of external pnp transistor is 100 and the base current of the limiter is 5ma, a rush current of 500ma flows into the regulators. when the wiring impedance is high, the power source voltage applied to ic tends to be varied by the rush current, so that the operation of ic may be adversely affected by the variation of the power source voltage. in these ics phase compensation is made for securing stable operation even when the load current is varied. select the capacitors c1 to c4 conecting the pin r out 1 to r out 4 with good frequency characteristics and small esr. be sure to connect a resistor with a resistance of about 100k between the base and the emitter for preventing the oscillation. set external parts as close as possible to the ic and minimize the connection between the parts and the ic. when using a capacitor connected to c d pin, use a schottky barrier diode (sbd) to discharge c d capacitor at the time of abrupt fluctuation of power source voltage.
47 applica tion for the cellular phones ( r 5ve 0 :optional mask v er sion) this optional mask version's application operates as follows. regulator 1, 2 : regulator 1 and 2 can be enabled and disabled through toggle input and cpu signal csw1. regulator 3 : regulator 3 can be enabled and disabled through toggle input and cpu signal csw2. regulator 4 : regulator 4 is always enabled by dry cells (when the v dd voltage is maintained higher than minimum operating voltage). the output of regulator 4 is not only the power source for cpu but also the level shift voltage of csw 1, 2 pins. therefor csw1, 2 pins can be direct - ly connected to cpu. detector 1, 2 : detector 1 and 2 monitor the v dd level and the output of regulator 4 respectively. furthermore detector 2 can generate the output-delay time (rise time delay) by connecting a capacitor to c d pin. tff : tff can be reset by the output of power-on-reset and detector 2 (through one shot pulse generator), while tff is in the reset state regulator 1, regulator 2 and regulator 3 are dis - abled. one shot pulse generator operation i n p u t 1 0 0 s o u t p u t r 5ve 0
48 application for the cellular phones ( r 5ve 0 ) 2 l e v e l s h i f t i b c 1 v d d m e c h a n i c a l s w i t c h r 5 q c 6 c s w 1 s b d c d g n d r t i s h o t p u l s e g e n e r a t o r r e g u l a t o r 2 r e g u l a t o r 3 r e g u l a t o r 4 d e t e c t o r 2 d e t e c t o r 1 t o g g l e i n p u t r o u t 1 i b c 2 r o u t 4 v s e n 1 d o u t v s e n 2 r e s e t r 6 r 1 c 1 c 2 c 3 r 2 t r t r r 4 r 3 m e m o r y / l o g i c u n i t t r a n s m i t t e r u n i t r e c e i v e r / a u d i o u n i t c p u r e s e t v c c i / o i / o i n t 1 3 1 0 9 8 7 6 4 5 1 1 1 2 1 3 1 4 1 5 1 6 c s w 2 c d r o u t 3 r o u t 2 c 4 c 5 l e v e l s h i f t r e g u l a t o r 2 c1,2,5=10 f/c3,4=0.1 f/c 6 =1 f/c d = 0.1 f r1,2,3,4=100k /r5=10k /r6=47 tr:2sb799(nec pnp type,h fe =100 to 200) sbd:ma717(panasonic) r 5ve 0
49 p a cka ge dimensions (unit: mm) ? 16pin ssop (0.8mm pitch) r 5ve 0 0 . 6 0 t y p . 6 . 8 0 . 3 0 . 4 0 . 2 6 . 2 0 . 3 4 . 4 0 . 2 0 . 8 0 0 . 1 5 + 0 . 1 0 . 0 5 0 . 3 6 0 . 1 1 . 5 0 . 1 0 . 0 5 0 . 0 5 0 . 8 0 . 1 0 0 . 1 2 m ? 16pin ssop (0.65mm pitch) 0 . 2 7 5 t y p . 5 . 1 0 . 3 0 . 5 0 . 2 6 . 4 0 . 3 4 . 4 0 . 2 0 . 1 5 + 0 . 1 0 . 0 5 0 . 2 2 0 . 1 . 0 . 1 1 . 1 5 0 . 1 0 . 6 5 0 . 1 5 0 . 1 5 m
r 5ve 0 50 t aping specifica tion (unit: mm) e 1 e 2 2 . 2 m a x . 0 . 3 0 . 1 1 2 . 0 0 . 1 6 . 9 1 6 . 0 0 . 3 7 . 5 0 . 1 1 . 7 5 0 . 1 4 . 0 0 . 1 2 . 0 0 . 1 7 . 2 1 . 5 + 0 . 1 0 u s e r d i r e c t i o n o f f e e d . ? 16pin ssop (0.8mm pitch) ? 16pin ssop (0.65mm pitch) e 1 e 2 2 . 7 m a x . 0 . 3 0 . 1 8 . 0 0 . 1 1 2 . 0 0 . 3 5 . 5 0 . 0 5 1 . 7 5 0 . 1 4 . 0 0 . 1 2 . 0 0 . 1 5 . 6 1 . 5 + 0 . 1 0 6 . 9 u s e r d i r e c t i o n o f f e e d .
ricoh company, ltd. electronic devices division headquarters 13-1, himemuro-cho, ikeda city, osaka 563-8501, japan phone 81-727-53-1111 fax 81-727-53-6011 yokohama office (international sales) 3-2-3, shin-yokohama, kohoku-ku, yokohama city, kanagawa 222-8530, japan phone 81-45-477-1697 fax 81-45-477-1694 ?1695 http://www.ricoh.co.jp/lsi/english/ ricoh corporation electronic devices division san jose office 3001 orchard parkway, san jose, ca 95134-2088, u.s.a. phone 1-408-432-8800 fax 1-408-432-8375

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